/**
 * 							Interrupt SRC Defination
 * @brief	interrrupt src define
 * @author	chy.
 * @note
 * @comment
 */
#ifndef _K_INT_S3C2440A_C_
#define _K_INT_S3C2440A_C_

#include "intertupt_s3c2440a.h"

/**
 * @BRIEF	:	Enable Specifac Interrupt
 * @PARAM	:	int_type	Interrtup type
 * @RETURN	:	void
 */
void k_int_irq_enable_type(unsigned int type)
{
	switch(type)
	{
		case INT_ADC:		// ADC EOC and Touch interrupt (INT_ADC_S/INT_TC) ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0x7fffffff;
		}
		break;
		case INT_RTC:   	// RTC alarm interrupt                            ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xbfffffff;
		}
		break;
		case INT_SPI:  		// SPI1 interrupt                                 ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xdfffffff;
		}
		break;
		case INT_UART0:		// UART0 Interrupt (ERR, RXD, and TXD)            ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xefffffff;
		}
		break;
		case INT_IIC:   	// IIC interrupt                                  ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xf7ffffff;
		}
		break;
		case INT_USBH:  	// USB Host interrupt                             ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfbffffff;
		}
		break;
		case INT_USBD:  	// USB Device interrupt                           ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfdffffff;
		}
		break;
		case INT_NFCON:   	// Nand Flash Control Interrupt                   ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfeffffff;
		}
		break;
		case INT_UART1: 	// UART1 Interrupt (ERR, RXD, and TXD)            ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xff7fffff;
		}
		break;
		case INT_SPI0:		// SPI0 interrupt                                 ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffbfffff;
		}
		break;
		case INT_SDI:		// SDI interrupt                                  ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffdfffff;
		}
		break;
		case INT_DMA3:  	// DMA channel 3 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffefffff;
		}
		break;
		case INT_DMA2:  	// DMA channel 2 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfff7ffff;
		}
		break;
		case INT_DMA1:  	// DMA channel 1 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffbffff;
		}
		break;
		case INT_DMA0:  	// DMA channel 0 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffdffff;
		}
		break;
		case INT_LCD:		// LCD interrupt (INT_FrSyn and INT_FiCnt)        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffeffff;
		}
		break;
		case INT_UART2:   	// Interrupt (ERR, RXD, and TXD) UART2            ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffff7fff;
		}
		break;
		case INT_TIMER4:   	// Timer4 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffbfff;
		}
		break;
		case INT_TIMER3:  	// Timer3 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffdfff;
		}
		break;
		case INT_TIMER2:  	// Timer2 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffefff;
		}
		break;
		case INT_TIMER1:  	// Timer1 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffff7ff;
		}
		break;
		case INT_TIMER0:  	// Timer0 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffbff;
		}
		break;
		case INT_WDT_AC97: 	// Watch-Dog timer interrupt(INT_WDT, INT_AC97)   ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffdff;
		}
		break;
		case INT_TICK: 		// RTC Time tick interrupt                        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffeff;
		}
		break;
		case nBATT_FLT:   	// Battery Fault interrupt                        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffff7f;
		}
		break;
		case INT_CAM:		// Camera Interface (INT_CAM_C, INT_CAM_P)        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffffbf;
		}
		break;
		case EINT8_23: 		// External interrupt 8 – 23                      ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffffdf;
		}
		break;
		case EINT4_7:		// External interrupt 4 – 7                       ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xffffffef;
		}
		break;
		case EINT3:			// External interrupt 3                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffff7;
		}
		break;
		case EINT2:			// External interrupt 2                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffffb;
		}
		break;
		case EINT1:			// External interrupt 1                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffffd;
		}
		break;
		case EINT0:			// External interrupt 0                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) &= 0xfffffffe;
		}
		break;
		case INT_AC97:     	// AC97 interrupt                                 INT_WDT_AC97
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x3fff;
		}
		break;
		case INT_WDT:     	// Watchdog interrupt                             INT_WDT_AC97
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x5fff;
		}
		break;
		case INT_CAM_P:    	// P-port capture interrupt in camera interface   INT_CAM
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x6fff;
		}
		break;
		case INT_CAM_C:    	// C-port capture interrupt in camera interface   INT_CAM
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x77ff;
		}
		break;
		case INT_ADC_S:    	// ADC interrupt                                  INT_ADC
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7bff;
		}
		break;
		case INT_TC:       	// Touch screen interrupt (pen up/down)           INT_ADC
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7dff;
		}
		break;
		case INT_ERR2:     	// UART2 error interrupt                          INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7eff;
		}
		break;
		case INT_TXD2:    	// UART2 transmit interrupt                       INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7f7f;
		}
		break;
		case INT_RXD2:     	// UART2 receive interrupt                        INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7fbf;
		}
		break;
		case INT_ERR1:     	// UART1 error interrupt                          INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7fdf;
		}
		break;
		case INT_TXD1:     	// UART1 transmit interrupt                       INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7fef;
		}
		break;
		case INT_RXD1:     	// UART1 receive interrupt                        INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7ff7;
		}
		break;
		case INT_ERR0:     	// UART0 error interrupt                          INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7ffb;
		}
		break;
		case INT_TXD0:     	// UART0 transmit interrupt                       INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7ffd;
		}
		break;
		case INT_RXD0:     	// UART0 receive interrupt                        INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) &= 0x7ffe;
		}
		break;
		default:
		return;
	}
}


/**
 * @BRIEF	:	Disable Specifac Interrupt
 * @PARAM	:	int_type	Interrtup type
 * @RETURN	:	void
 */
void k_int_irq_diable_type(unsigned int type)
{
	switch(type)
	{
		case INT_ADC:		// ADC EOC and Touch interrupt (INT_ADC_S/INT_TC) ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_ADC_MSK_AND_CIF;
		}
		break;
		case INT_RTC:   	// RTC alarm interrupt                            ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_RTC_MSK_AND_CIF;
		}
		break;
		case INT_SPI:  		// SPI1 interrupt                                 ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_SPI1_MSK_AND_CIF;
		}
		break;
		case INT_UART0:		// UART0 Interrupt (ERR, RXD, and TXD)            ARB5
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_UART0_MSK_AND_CIF;
		}
		break;
		case INT_IIC:   	// IIC interrupt                                  ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_IIC_MSK_AND_CIF;
		}
		break;
		case INT_USBH:  	// USB Host interrupt                             ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_USBH_MSK_AND_CIF;
		}
		break;
		case INT_USBD:  	// USB Device interrupt                           ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_USBD_MSK_AND_CIF;
		}
		break;
		case INT_NFCON:   	// Nand Flash Control Interrupt                   ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_NFCON_MSK_AND_CIF;
		}
		break;
		case INT_UART1: 	// UART1 Interrupt (ERR, RXD, and TXD)            ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_UART1_MSK_AND_CIF;
		}
		break;
		case INT_SPI0:		// SPI0 interrupt                                 ARB4
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_SPI0_MSK_AND_CIF;
		}
		break;
		case INT_SDI:		// SDI interrupt                                  ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_SDI_MSK_AND_CIF;
		}
		break;
		case INT_DMA3:  	// DMA channel 3 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_DMA3_MSK_AND_CIF;
		}
		break;
		case INT_DMA2:  	// DMA channel 2 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_DMA2_MSK_AND_CIF;
		}
		break;
		case INT_DMA1:  	// DMA channel 1 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_DMA1_MSK_AND_CIF;
		}
		break;
		case INT_DMA0:  	// DMA channel 0 interrupt                        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_DMA0_MSK_AND_CIF;
		}
		break;
		case INT_LCD:		// LCD interrupt (INT_FrSyn and INT_FiCnt)        ARB3
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_LCD_MSK_AND_CIF;
		}
		break;
		case INT_UART2:   	// Interrupt (ERR, RXD, and TXD) UART2            ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_UART2_MSK_AND_CIF;
		}
		break;
		case INT_TIMER4:   	// Timer4 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TIMER4_MSK_AND_CIF;
		}
		break;
		case INT_TIMER3:  	// Timer3 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TIMER3_MSK_AND_CIF;
		}
		break;
		case INT_TIMER2:  	// Timer2 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TIMER2_MSK_AND_CIF;
		}
		break;
		case INT_TIMER1:  	// Timer1 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TIMER1_MSK_AND_CIF;
		}
		break;
		case INT_TIMER0:  	// Timer0 interrupt                               ARB2
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TIMER0_MSK_AND_CIF;
		}
		break;
		case INT_WDT_AC97: 	// Watch-Dog timer interrupt(INT_WDT, INT_AC97)   ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_WDT_AC97_MSK_AND_CIF;
		}
		break;
		case INT_TICK: 		// RTC Time tick interrupt                        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_TICK_MSK_AND_CIF;
		}
		break;
		case nBATT_FLT:   	// Battery Fault interrupt                        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= nBATT_FLT_MSK_AND_CIF;
		}
		break;
		case INT_CAM:		// Camera Interface (INT_CAM_C, INT_CAM_P)        ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= INT_CAM_MSK_AND_CIF;
		}
		break;
		case EINT8_23: 		// External interrupt 8 – 23                      ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT8_23_MSK_AND_CIF;
		}
		break;
		case EINT4_7:		// External interrupt 4 – 7                       ARB1
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT4_7_MSK_AND_CIF;
		}
		break;
		case EINT3:			// External interrupt 3                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT3_MSK_AND_CIF;
		}
		break;
		case EINT2:			// External interrupt 2                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT2_MSK_AND_CIF;
		}
		break;
		case EINT1:			// External interrupt 1                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT1_MSK_AND_CIF;
		}
		break;
		case EINT0:			// External interrupt 0                           ARB0
		{
			(*(unsigned int *)INT_PORT_INTMSK) |= EINT0_MSK_AND_CIF;
		}
		break;
		case INT_AC97:     	// AC97 interrupt                                 INT_WDT_AC97
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x4000;
		}
		break;
		case INT_WDT:     	// Watchdog interrupt                             INT_WDT_AC97
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x2000;
		}
		break;
		case INT_CAM_P:    	// P-port capture interrupt in camera interface   INT_CAM
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x1000;
		}
		break;
		case INT_CAM_C:    	// C-port capture interrupt in camera interface   INT_CAM
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0800;
		}
		break;
		case INT_ADC_S:    	// ADC interrupt                                  INT_ADC
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0400;
		}
		break;
		case INT_TC:       	// Touch screen interrupt (pen up/down)           INT_ADC
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0200;
		}
		break;
		case INT_ERR2:     	// UART2 error interrupt                          INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0100;
		}
		break;
		case INT_TXD2:    	// UART2 transmit interrupt                       INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0080;
		}
		break;
		case INT_RXD2:     	// UART2 receive interrupt                        INT_UART2
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0040;
		}
		break;
		case INT_ERR1:     	// UART1 error interrupt                          INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0020;
		}
		break;
		case INT_TXD1:     	// UART1 transmit interrupt                       INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0010;
		}
		break;
		case INT_RXD1:     	// UART1 receive interrupt                        INT_UART1
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0008;
		}
		break;
		case INT_ERR0:     	// UART0 error interrupt                          INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0004;
		}
		break;
		case INT_TXD0:     	// UART0 transmit interrupt                       INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0002;
		}
		break;
		case INT_RXD0:     	// UART0 receive interrupt                        INT_UART0
		{
			(*(unsigned int *)INT_PORT_INTSUBMSK) |= 0x0001;
		}
		break;
		default:
		return;
	}
}

/**
 * @BRIEF	:	Clean Specifac Interrupt
 * @PARAM	:	int_type	Interrtup type
 * @RETURN	:	void
 */
void k_int_irq_clean(unsigned int type)
{
	switch(type)
	{
		case INT_ADC:	 		// ADC EOC and Touch interrupt (INT_ADC_S/INT_TC) ARB5
			INT_CLEAN_SRCPND_INT(INT_ADC_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_ADC_MSK_AND_CIF);
		break;
		case INT_RTC:   		// RTC alarm interrupt                            ARB5
			INT_CLEAN_SRCPND_INT(INT_RTC_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_RTC_MSK_AND_CIF);
		break;
		case INT_SPI1:  		// SPI1 interrupt                                 ARB5
			INT_CLEAN_SRCPND_INT(INT_SPI1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_SPI1_MSK_AND_CIF);
		break;
		case INT_UART0:   		// UART0 Interrupt (ERR, RXD, and TXD)            ARB5
			INT_CLEAN_SRCPND_INT(INT_UART0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART0_MSK_AND_CIF);
		break;
		case INT_IIC:   		// IIC interrupt                                  ARB4
			INT_CLEAN_SRCPND_INT(INT_IIC_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_IIC_MSK_AND_CIF);
		break;
		case INT_USBH:  		// USB Host interrupt                             ARB4
			INT_CLEAN_SRCPND_INT(INT_USBH_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_USBH_MSK_AND_CIF);
		break;
		case INT_USBD:  		// USB Device interrupt                           ARB4
			INT_CLEAN_SRCPND_INT(INT_USBD_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_USBD_MSK_AND_CIF);
		break;
		case INT_NFCON:   		// Nand Flash Control Interrupt                   ARB4
			INT_CLEAN_SRCPND_INT(INT_NFCON_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_NFCON_MSK_AND_CIF);
		break;
		case INT_UART1: 		// UART1 Interrupt (ERR, RXD, and TXD)            ARB4
			INT_CLEAN_SRCPND_INT(INT_UART1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART1_MSK_AND_CIF);
		break;
		case INT_SPI0:			// SPI0 interrupt                                 ARB4
			INT_CLEAN_SRCPND_INT(INT_SPI0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_SPI0_MSK_AND_CIF);
		break;
		case INT_SDI:			// SDI interrupt                                  ARB3
			INT_CLEAN_SRCPND_INT(INT_SDI_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_SDI_MSK_AND_CIF);
		break;
		case INT_DMA3:  		// DMA channel 3 interrupt                        ARB3
			INT_CLEAN_SRCPND_INT(INT_DMA3_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_DMA3_MSK_AND_CIF);
		break;
		case INT_DMA2:  		// DMA channel 2 interrupt                        ARB3
			INT_CLEAN_SRCPND_INT(INT_DMA2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_DMA2_MSK_AND_CIF);
		break;
		case INT_DMA1:  		// DMA channel 1 interrupt                        ARB3
			INT_CLEAN_SRCPND_INT(INT_DMA1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_DMA1_MSK_AND_CIF);
		break;
		case INT_DMA0:  		// DMA channel 0 interrupt                        ARB3
			INT_CLEAN_SRCPND_INT(INT_DMA0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_DMA0_MSK_AND_CIF);
		break;
		case INT_LCD:			// LCD interrupt (INT_FrSyn and INT_FiCnt)        ARB3
			INT_CLEAN_SRCPND_INT(INT_LCD_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_LCD_MSK_AND_CIF);
		break;
		case INT_UART2:   		// Interrupt (ERR, RXD, and TXD) UART2            ARB2
			INT_CLEAN_SRCPND_INT(INT_UART2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART2_MSK_AND_CIF);
		break;
		case INT_TIMER4:   		// Timer4 interrupt                               ARB2
			INT_CLEAN_SRCPND_INT(INT_TIMER4_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TIMER4_MSK_AND_CIF);
		break;
		case INT_TIMER3:  		// Timer3 interrupt                               ARB2
			INT_CLEAN_SRCPND_INT(INT_TIMER3_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TIMER3_MSK_AND_CIF);
		break;
		case INT_TIMER2:  		// Timer2 interrupt                               ARB2
			INT_CLEAN_SRCPND_INT(INT_TIMER2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TIMER2_MSK_AND_CIF);
		break;
		case INT_TIMER1:  		// Timer1 interrupt                               ARB2
			INT_CLEAN_SRCPND_INT(INT_TIMER1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TIMER1_MSK_AND_CIF);
		break;
		case INT_TIMER0:  		// Timer0 interrupt                               ARB2
			INT_CLEAN_SRCPND_INT(INT_TIMER0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TIMER0_MSK_AND_CIF);
		break;
		case INT_WDT_AC97:  	// Watch-Dog timer interrupt(INT_WDT, INT_AC97)   ARB1
			INT_CLEAN_SRCPND_INT(INT_WDT_AC97_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_WDT_AC97_MSK_AND_CIF);
		break;
		case INT_TICK: 			// RTC Time tick interrupt                        ARB1
			INT_CLEAN_SRCPND_INT(INT_TICK_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_TICK_MSK_AND_CIF);
		break;
		case nBATT_FLT:   		// Battery Fault interrupt                        ARB1
			INT_CLEAN_SRCPND_INT(nBATT_FLT_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(nBATT_FLT_MSK_AND_CIF);
		break;
		case INT_CAM:			// Camera Interface (INT_CAM_C, INT_CAM_P)        ARB1
			INT_CLEAN_SRCPND_INT(INT_CAM_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_CAM_MSK_AND_CIF);
		break;
		case EINT8_23:  		// External interrupt 8 – 23                      ARB1
			INT_CLEAN_SRCPND_INT(EINT8_23_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT8_23_MSK_AND_CIF);
		break;
		case EINT4_7:			// External interrupt 4 – 7                       ARB1
			INT_CLEAN_SRCPND_INT(EINT4_7_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT4_7_MSK_AND_CIF);
		break;
		case EINT3:				// External interrupt 3                           ARB0
			INT_CLEAN_SRCPND_INT(EINT3_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT3_MSK_AND_CIF);
		break;
		case EINT2:				// External interrupt 2                           ARB0
			INT_CLEAN_SRCPND_INT(EINT2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT2_MSK_AND_CIF);
		break;
		case EINT1:				// External interrupt 1                           ARB0
			INT_CLEAN_SRCPND_INT(EINT1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT1_MSK_AND_CIF);
		break;
		case EINT0:				// External interrupt 0                           ARB0
			INT_CLEAN_SRCPND_INT(EINT0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(EINT0_MSK_AND_CIF);
		break;
		case INT_AC97:      	// AC97 interrupt                                 INT_WDT_AC97
			INT_CLEAN_SUBSRCPND_INT(INT_AC97_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_WDT_AC97_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_WDT_AC97_MSK_AND_CIF);
		break;
		case INT_WDT:     		// Watchdog interrupt                             INT_WDT_AC97
			INT_CLEAN_SUBSRCPND_INT(INT_WDT_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_WDT_AC97_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_WDT_AC97_MSK_AND_CIF);
		break;
		case INT_CAM_P:     	// P-port capture interrupt in camera interface   INT_CAM
			INT_CLEAN_SUBSRCPND_INT(INT_CAM_P_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_CAM_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_CAM_MSK_AND_CIF);
		break;
		case INT_CAM_C:    		// C-port capture interrupt in camera interface   INT_CAM
			INT_CLEAN_SUBSRCPND_INT(INT_CAM_C_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_CAM_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_CAM_MSK_AND_CIF);
		break;
		case INT_ADC_S:    		// ADC interrupt                                  INT_ADC
			INT_CLEAN_SUBSRCPND_INT(INT_ADC_S_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_ADC_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_ADC_MSK_AND_CIF);
		break;
		case INT_TC:       		// Touch screen interrupt (pen up/down)           INT_ADC
			INT_CLEAN_SUBSRCPND_INT(INT_TC_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_ADC_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_ADC_MSK_AND_CIF);
		break;
		case INT_ERR2:      	// UART2 error interrupt                          INT_UART2
			INT_CLEAN_SUBSRCPND_INT(INT_ERR2_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART2_MSK_AND_CIF);
		break;
		case INT_TXD2:    		// UART2 transmit interrupt                       INT_UART2
			INT_CLEAN_SUBSRCPND_INT(INT_TXD2_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART2_MSK_AND_CIF);
		break;
		case INT_RXD2:     		// UART2 receive interrupt                        INT_UART2
			INT_CLEAN_SUBSRCPND_INT(INT_RXD2_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART2_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART2_MSK_AND_CIF);
		break;
		case INT_ERR1:     		// UART1 error interrupt                          INT_UART1
			INT_CLEAN_SUBSRCPND_INT(INT_ERR1_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART1_MSK_AND_CIF);
		break;
		case INT_TXD1:     		// UART1 transmit interrupt                       INT_UART1
			INT_CLEAN_SUBSRCPND_INT(INT_TXD1_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART1_MSK_AND_CIF);
		break;
		case INT_RXD1:     		// UART1 receive interrupt                        INT_UART1
			INT_CLEAN_SUBSRCPND_INT(INT_RXD1_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART1_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART1_MSK_AND_CIF);
		break;
		case INT_ERR0:     		// UART0 error interrupt                          INT_UART0
			INT_CLEAN_SUBSRCPND_INT(INT_ERR0_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART0_MSK_AND_CIF);
		break;
		case INT_TXD0:     		// UART0 transmit interrupt                       INT_UART0
			INT_CLEAN_SUBSRCPND_INT(INT_TXD0_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART0_MSK_AND_CIF);
		break;
		case INT_RXD0     		// UART0 receive interrupt                        INT_UART0
			INT_CLEAN_SUBSRCPND_INT(INT_RXD0_MSK_AND_CIF_SUB);
			INT_CLEAN_SRCPND_INT(INT_UART0_MSK_AND_CIF);
			INT_CLEAN_INTPND_INT(INT_UART0_MSK_AND_CIF);
		break;
		default:
		return;
	}
}

/**
 * @BRIEF	:	Get current interrupt type
 * @PARAM	:	void
 * @RETURN	:	int_type	Interrtup type
 * @NOTE	:	this function should clear the interrupt flag bits if nessasery!
 */
unsigned int k_int_get_cur_irq_type(void)
{
	unsigned int *ptype = (unsigned int *)INT_PORT_INTOFFSET;
	unsigned int type = *ptype;

	// read SUBSRCPND, no matter whether sub interrupt occured!
	unsigned int subsrc = *((unsigned int *)INT_PORT_SUBSRCPND);
	switch(type)
	{
		case INT_ADC_OFFT:		// need read sub interrupt
		{
			// we just need the corresponding bits for current interrupt src
			subsrc &= 0x600;
			switch(subsrc)
			{
				case 0x600:
				{
					// both interrupt has occured.but we just read one of them, we aussume TC priority higher than INT_ADC_S
					// clean srcpnd flat of this interrupt
					k_int_irq_clean(INT_TC);
					return INT_TC;
				}
				break;
				case 0x200:
				{
					// INT_TC
					k_int_irq_clean(INT_TC);
					return INT_TC;
				}
				break;
				case 0x400:
				{
					// INT_ADC_S
					k_int_irq_clean(INT_ADC_S);
					return INT_ADC_S;
				}
				break;
				default:
				// there must be some errors!
				return 0xffffffff;
			}
		}
		break;
		case INT_RTC_OFFT:
			k_int_irq_clean(INT_RTC);
			return;
		break;
		case INT_SPI1_OFFT:
			k_int_irq_clean(INT_SPI1);
			return INT_SPI1;
		break;
		case INT_UART0_OFFT:	// need read sub interrupt
		{
			subsrc &= 0x7;
			switch(subsrc)
			{
				case 0x7:
				{
					// all sub interrupt has occured. we choose one.we assume INT_ERR0 priority is the highest
					// clean
					k_int_irq_clean(INT_ERR0);
					return INT_ERR0;
				}
				break;
				case 0x6:
				{
					// INT_ERR0 and INT_TXD0
					k_int_irq_clean(INT_ERR0);
					return INT_ERR0;
				}
				break;
				case 0x5:
				{
					// INT_ERR0 and INT_RXD0
					k_int_irq_clean(INT_ERR0);
					return INT_ERR0;
				}
				break;
				case 0x4:
				{
					// INT_ERR0
					k_int_irq_clean(INT_ERR0);
					return INT_ERR0;
				}
				break;
				case 0x3:
				{
					// INT_TXD0 and INT_RXD0
					k_int_irq_clean(INT_RXD0);
					return INT_RXD0;
				}
				break;
				case 0x2:
				{
					// INT_TXD0
					k_int_irq_clean(INT_TXD0);
					return INT_TXD0;
				}
				break;
				case 0x1:
				{
					// INT_RXD0
					k_int_irq_clean(INT_RXD0);
					return INT_RXD0;
				}
				break;
				default:
				return 0xffffffff;
			}
		}
		break;
		case INT_IIC_OFFT:
			k_int_irq_clean(INT_IIC);
			return INT_IIC;
		break;
		case INT_USBH_OFFT:
			k_int_irq_clean(INT_USBH);
			return INT_USBH;
		break;
		case INT_USBD_OFFT:
			k_int_irq_clean(INT_USBD);
			return INT_USBD;
		break;
		case INT_NFCON_OFFT:
			k_int_irq_clean(INT_NFCON);
			return INT_NFCON;
		break;
		case INT_UART1_OFFT:	// need read sub interrupt
		{
			subsrc &= 0x38;
			switch(subsrc)
			{
				case 0x38:
				{
					// all sub interrupt has occured. we choose one.we assume INT_ERR1 priority is the highest
					// clean
					k_int_irq_clean(INT_ERR1);
					return INT_ERR1;
				}
				break;
				case 0x30:
				{
					// INT_ERR1 and INT_TXD1
					k_int_irq_clean(INT_ERR1);
					return INT_ERR1;
				}
				break;
				case 0x28:
				{
					// INT_ERR1 and INT_RXD1
					k_int_irq_clean(INT_ERR1);
					return INT_ERR1;
				}
				break;
				case 0x20:
				{
					// INT_ERR1
					k_int_irq_clean(INT_ERR1);
					return INT_ERR1;
				}
				break;
				case 0x18:
				{
					// INT_TXD1 and INT_RXD1
					k_int_irq_clean(INT_RXD1);
					return INT_RXD1;
				}
				break;
				case 0x10:
				{
					// INT_TXD1
					k_int_irq_clean(INT_TXD1);
					return INT_TXD1;
				}
				break;
				case 0x8:
				{
					// INT_RXD1
					k_int_irq_clean(INT_RXD1);
					return INT_RXD1;
				}
				break;
				default:
				return 0xffffffff;
			}
		}
		break;
		case INT_SPI0_OFFT:
			k_int_irq_clean(INT_SPI0);
			return INT_SPI0;
		break;
		case INT_SDI_OFFT:
			k_int_irq_clean(INT_SDI);
			return INT_SDI;
		break;
		case INT_DMA3_OFFT:
			k_int_irq_clean(INT_DMA3);
			return INT_DMA3;
		break;
		case INT_DMA2_OFFT:
			k_int_irq_clean(INT_DMA2);
			return INT_DMA2;
		break;
		case INT_DMA1_OFFT:
			k_int_irq_clean(INT_DMA1);
			return INT_DMA1;
		break;
		case INT_DMA0_OFFT:
			k_int_irq_clean(INT_DMA0);
			return INT_DMA0;
		break;
		case INT_LCD_OFFT:
			k_int_irq_clean(INT_LCD);
			return INT_LCD;
		break;
		case INT_UART2_OFFT:	// need read sub interrupt
		{
			subsrc &= 0x1c0;
			switch(subsrc)
			{
				case 0x1c0:
				{
					// all sub interrupt has occured. we choose one.we assume INT_ERR2 priority is the highest
					// clean
					k_int_irq_clean(INT_ERR2);
					return INT_ERR2;
				}
				break;
				case 0x180:
				{
					// INT_ERR2 and INT_TXD2
					k_int_irq_clean(INT_ERR2);
					return INT_ERR2;
				}
				break;
				case 0x140:
				{
					// INT_ERR2 and INT_RXD2
					k_int_irq_clean(INT_ERR2);
					return INT_ERR2;
				}
				break;
				case 0x100:
				{
					// INT_ERR2
					k_int_irq_clean(INT_ERR2);
					return INT_ERR2;
				}
				break;
				case 0xc0:
				{
					// INT_TXD2 and INT_RXD2
					k_int_irq_clean(INT_RXD2);
					return INT_RXD2;
				}
				break;
				case 0x80:
				{
					// INT_TXD2
					k_int_irq_clean(INT_TXD2);
					return INT_TXD2;
				}
				break;
				case 0x40:
				{
					// INT_RXD2
					k_int_irq_clean(INT_RXD2);
					return INT_RXD2;
				}
				break;
				default:
				return 0xffffffff;
			}
		}
		break;
		case INT_TIMER4_OFFT:
			k_int_irq_clean(INT_TIMER4);
			return INT_TIMER4;
		break;
		case INT_TIMER3_OFFT:
			k_int_irq_clean(INT_TIMER3);
			return INT_TIMER3;
		break;
		case INT_TIMER2_OFFT:
			k_int_irq_clean(INT_TIMER2);
			return INT_TIMER2;
		break;
		case INT_TIMER1_OFFT:
			k_int_irq_clean(INT_TIMER1);
			return INT_TIMER1;
		break;
		case INT_TIMER0_OFFT:
			k_int_irq_clean(INT_TIMER0);
			return INT_TIMER0;
		break;
		case INT_WDT_AC97_OFFT:	// need read sub interrupt
		{
			subsrc &= 0x6000;
			switch(subsrc)
			{
				case 0x6000:
				{
					// both INT_WDT and INT_AC97, we assume that INT_WDT higher
					k_int_irq_clean(INT_WDT);
					return INT_WDT;
				}
				break;
				case 0x4000:
				{
					k_int_irq_clean(INT_AC97);
					return INT_AC97;
				}
				break;
				case 0x2000:
				{
					k_int_irq_clean(INT_WDT);
					return INT_WDT;
				}
				break;
				default:
				return 0xffffffff;
			}
		}
		break;
		case INT_TICK_OFFT:
			k_int_irq_clean(INT_TICK);
			return INT_TICK;
		break;
		case nBATT_FLT_OFFT:
			k_int_irq_clean(nBATT_FLT);
			return nBATT_FLT;
		break;
		case INT_CAM_OFFT:		// need read sub interrupt
		{
			subsrc &= 0x1800;
			switch(subsrc)
			{
				case 0x1800:
				{
					// INT_CAM_P and INT_CAM_C, we assume INT_CAM_C higher
					k_int_irq_clean(INT_CAM_C);
					return INT_CAM_C;
				}
				break;
				case 0x1000:
				{
					// INT_CAM_P
					k_int_irq_clean(INT_CAM_P);
					return INT_CAM_P;
				}
				break;
				case 0x800:
				{
					k_int_irq_clean(INT_CAM_C);
					return INT_CAM_C;
				}
				break;
				default:
				return 0xffffffff;
			}
		}
		break;
		case EINT8_23_OFFT:
			k_int_irq_clean(EINT8_23);
			return EINT8_23;
		break;
		case EINT4_7_OFFT:
			k_int_irq_clean(EINT4_7);
			return EINT4_7;
		break;
		case EINT3_OFFT:
			k_int_irq_clean(EINT3);
			return EINT3;
		break;
		case EINT2_OFFT:
			k_int_irq_clean(EINT2);
			return EINT2;
		break;
		case EINT1_OFFT:
			k_int_irq_clean(EINT1);
			return EINT1;
		break;
		case EINT0_OFFT:
			k_int_irq_clean(EINT0);
			return EINT0;
		break;
		default:
		{
			// there must be some thing error.May be the port address it wrong!
		}
		return;
	}
}

/**
 * @BRIEF	:	Set Interrupt Priority
 * @PARAM	:	priority value
 * @RETURN	:	void
 * @NOTE	:	This function just write the value to the correspounding rigister
 */
void k_init_set_irq_priority(unsigned int priority)
{
	(*(unsigned int *)INT_PORT_PRIORITY) = priority;
}

#endif /* _K_INT_S3C2440A_C_ */